1. Field of the Invention
The present invention relates to a disk reproduction apparatus for an optical disk such as a compact disk (CD), a digital versatile disk (DVD), or the like, and particularly, to a data slice circuit for a reproduction apparatus capable of sequentially varying its reproduction speed.
2. Discussion of the Background
In the field of audio devices, developments are presently made for a digital recording/reproducing system. Since this system performs recording/reproducing at a high density with a high fidelity, audio signals are converted into digital signals by means of a PCM (Pulse Code Modulation) technique, which are recorded on a recording medium such as a disk or a magnetic tape and are also reproduced. Particularly, in case of a CD which is widely used now, bit columns corresponding to digital data are formed on a disk having a diameter of 12 cm.
In the CD, digital data (main information data) obtained by PCM-encoding analog audio signals in units of 16-bit is recorded. The digital data is recorded in a manner of repeating frames, on condition that eight bits constitute one symbol and twenty four symbols constitute one frame. In the CD, a CIRC (Cross Interleave Reed-Solomon Code) is used as an error correction code.
Specifically, digital data consisting of 24 symbols is supplied to a C2-sequence parity generator circuit and parity data consisting of 4 symbols Q for correcting a C2-sequence error is generated. The digital data and the parity symbol Q are supplied to a C1-sequence parity generator circuit through an interleave circuit, and parity symbol P consisting of 4 symbols for correcting a C1-sequence error is generated. Data of 32 symbols consisting of the data of 24 symbols, the parity symbol P of 4 symbols, and the parity symbol Q of 4 symbols is added with sub-code data of 8-bit (consisting of one symbol). The sub-code data and the data of 32 symbols are subjected to EFM (Eight Fourteen Modulation). Margins of 3-bit are added between these symbols each being of 14-bit, and further, a frame synchronization data of 24-bit is added to the top. Thus, data of 588-bit is recorded as one frame onto a disk. In this case, since the bit clock is 4.32 MHz, data is recorded onto a disk at 136 .mu.sec (7.35 KHz) per frame. As for sub-code data, one sub-code frame consists of 98 frames, and sub-code data is recorded onto a disk at 75 Hz (10.3 msec) per sub-code frame.
In a disk reproduction apparatus for reproducing data from a CD, a CD is rotated at a constant linear velocity (CLV) by a motor control circuit and a motor. An example of this kind of disk reproduction apparatus which has been conventionally known is an apparatus described in U.S. Pat. No. 5,526,339 by the same assignor as the present invention.
The conventional disk reproduction apparatus disclosed in the patent is provided with an optical pickup element including a semiconductor laser, a photoelectric transducer, and the like. The optical pickup element reads data recorded on a CD, by linearly tracking the disk being rotated by a disk motor, from the inner circumferential side to the outer circumferential side. The data (or a current signal) thus read is supplied to an amplifier. The amplifier converts the current signal into a signal of a wide range as a voltage signal (which will hereinafter referred to as an RF signal) and supplies the converted signal to a data slice circuit. The data slice circuit binarizes a reproduction signal and supplies the signal as a EFM signal to a PLL (Phase Locked Loop) circuit and a data processing circuit. The data processing circuit separates a synchronization signal from the EFM signal, and thereafter, performs EFM demodulation, to separates therefrom a sub-code data component and a data component of 32 symbols including parity symbol P and parity symbol Q. Subsequently, the data thus EFM-demodulated is written into a memory by a clock signal generated from the PLL circuit. The data thus written into the memory is read from the memory by a system reference clock signal of a constant frequency generated with use of a quartz oscillator, thereby to absorb a change of time axis caused due to the motor. The data thus read from the memory is subjected to error correction, and is thereafter outputted as digital data of 16-bit.
Change of the reproduction speed is carried out by a system controller. The system controller generates a reproduction speed control signal (which will be hereinafter referred to as a HS). The HS signal instructs, for example, a normal reproduction speed (1.times.-speed), or a twice higher speed than a reference speed (2.times.-speed). The HS signal is supplied to the data processing circuit and the motor control circuit, and the processing speed and the disk reproduction speed are switched to aimed velocities. Also, the HS signal is supplied to the data slice circuit, and the data slice circuit changes the control frequency range so as to correspond to the reproduction speed, in response to the HS signal.
The data slice circuit compares the RF signal with the reference voltage, and converts the RF signal into binary data (a binarized signal), e.g., a EFM signal. An up/down counter counts a period of binarized data "0" and a period of data "1", and outputs differential data therebetween.
A count clock of the up/down counter is a clock signal generated by a PLL circuit, based on a EFM signal. The clock signal is synchronized with the reproduction speed of data.
The differential data outputted from the up/down counter is supplied to a digital/analog converter. The digital/analog converter converts the differential data into an analogue voltage and feeds back the analog voltage as a reference voltage described above, to a comparator. The comparator binarizes a RF signal by the reference voltage thus fed back, thereby to control the period of "0" to be equal to the period of data "1".
The data slice circuit thus feeds back a count result so that the period of data "0" is equal to the period of data "1".
If the frequency range in the feed-back loop described above is too low, the slice level cannot follow a change of an amplitude of the RF signal when the amplitude of the RF signal changes. Inversely, if the frequency range is too high, the slice level changes following the amplitude of the RF signal having a very small slice level if the frequency range is too high, the EFM signal after slice increases jitters.
From the reasons describe above, frequency range setting must be carried out for a data slice circuit. However, in a conventional data slice circuit, it is difficult to design a frequency range for one single data slice circuit itself since the EFM signal and the clock signal inputted to the up/down counter are synchronized with each other.